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Session 1: Strategies and Techniques for Reducing Turnaround Time and Power 65-nm Design Tape-Out in 6 weeks, Adapteva Inc. Multi-Mode/Multi-Corner Analysis Using Talus Flow Manager, Wipro Session 2: Challenges of Full-Flow RTL-to-GDSII SoC Implementation Comparing Crosstalk Delay Calculations in Talus and Prime Time-SI, Qthink Leveraging Quartz DRC Capabilities on Advanced Server Processors in 45 nm and Beyond, IBM Session 3: Taming the Dragon – Managing Multi-Scenario Analysis and Timing Closure Timing Closure Challenges and Solutions, Magma Accelerating Timing Closure on Large, Complex Nanometer Designs, Server Engines
Session 1: Strategies and Techniques for Reducing Turnaround Time and Power
Session 2: Challenges of Full-Flow RTL-to-GDSII SoC Implementation
Session 3: Taming the Dragon – Managing Multi-Scenario Analysis and Timing Closure
Tutorial
Session 1: Testing 1, 2, 3: The Latest DFT Techniques
Session 2: Leveraging Faster, More Accurate Circuit Simulation
Session 3: Advances in Analog Design and IC Failure Analysis
Session 1: Strategies and Techniques for Reducing Turnaround Time and Power 65-nm Design Tape-Out in 6 Weeks Author(s): Andreas Olofsson, President and Architect, Adapteva Inc.
Abstract:The future of systems-on-chip (SoCs) is low power. To get there, both a new computing architecture and programming methodology are needed. Adapteva has developed a novel solution to both challenges with a processor architecture capable of 50GFLOP/W. With the right people and tools SoCs don't have to cost $75 million. In this presentation, you’ll see how we went from new Magma users to taping out a multimillion-gate SoC in 6 weeks. We’ll show you how we used the full Magma RTL-to-GDSII hierarchical flow including the Talus Flow Manager and Quartz DRC/LVS. Lessons learned on the user-defined fully abutted approach will be shared, as well as an overview of our design architecture.
Multi-Mode/Multi-Corner Analysis Using Talus Flow Manager Author(s): Aravind Chandramohan, Programmer Analyst, Wipro Technologies Abstract: This paper explains on-chip-variation (OCV) based multi-mode/multi-corner (MMMC) optimization using the Talus Flow Manager from netlist to tapeout for multi-floorplan/multi-power domain design. The approach taken and experimental results for achieving better quality of results (QoR), runtime reduction and correlation results with sign-off are explained with metrics collected at every stage. The results are compared with similar taped out design that used merged mode optimization. The design had a complex clock tree mechanism with multiple clock generation logics and intra clock domains which prompted a different clock tree synthesis methodology to be used. The scenario identification for different stages including hold fixing is also discussed.
Session 2: Challenges of Full-Flow RTL-to-GDSII SoC Implementation Comparing Crosstalk Delay Calculations in Talus and PrimeTime-SI Author(s): Siobhan Barry, Senior Design Engineer and Bryan Heard, Chief Technology Officer, QThink Abstract: Even though many designs use Talus Vortex for sign-off timing, some customers are reluctant to make the change from PrimeTime-SI (PTSI). An oft mentioned concern is the difference in calculated crosstalk delay. A large proportion of these differences can be attributed to how the aggressor nets are selected. This presentation discusses the strategies used by Talus Vortex and PTSI to filter out victim and aggressor nets so that they are not considered during crosstalk delay analysis. Descriptions of the commands used to configure the Talus crosstalk delay calculations and their impact on runtime will also be presented along with some commands that can be used to analyze the resulting crosstalk delay.
Leveraging Quartz DRC Capabilities on Advanced Server Processors in 45 nm and Beyond, IBMAuthor(s):
Session 3: Taming the Dragon: Managing Multi-Scenario Analysis and Timing Closure Timing Closure Challenges and Solutions Presenter: Daniel Blong, Technical Marketing Manager, Magma Abstract:Timing closure today is more challenging than ever before. Design teams are working on bigger chips, with more STA scenarios, with fewer people. Is there any hope on the horizon? Come have an open discussion with Magma R&D about new ideas for approaches on tackling the trials or timing closure faster (and smarter).
Accelerating Timing Closure on Large, Complex Nanometer Designs Author(s): Ravi Arikapudi, Physical Design Manager, Server Engines
Abstract: This paper will describe the implementation of complex, hierarchical chips at 65 nm and below. With over 10 blocks – each averaging ~1.5 million instances – and a large number of timing modes and process, voltage and temperature (PVT) corners, we knew that achieving timing closure in a reasonable amount of time would be a challenge. That coupled with the high cost of the machines and number of STA licenses we would require caused us to look at new and interesting approaches from Magma that could scale with our technology node migration and increasing design complexity.
Solving Design Challenges Visually with the Talus Visual Volcano Presenter: Rob Knoth, Technical Product Manager, Magma While IC design complexity increases, engineering teams have remained the same size or have shrunk. Today’s engineers have to be exponentially more productive to get their jobs done. Talus Vortex helps improve designer productivity by delivering improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows. But things don’t always go according to plan and schedule. To accelerate design debugging and improve communication between team members, Magma provides the Talus Visual Volcano™. This visual analysis environment integrates and presents all design and analysis data via a common display, allowing you to make better design decisions faster. In this presentation, we’ll show you how the Talus Visual Volcano allows you to:
Session 1: Testing 1, 2, 3: The Latest DFT Techniques Talus Design with Scan Test Compression Author(s): Debo Sekoni, Senior Design Engineer, DFT, AltaSens, Inc, and Bill Keller, Applications Engineer Consultant, Mentor GraphicsAbstract: Design-for-test (DFT) engineers have seen the length and complexity of integrated circuit scan tests expand exponentially in recent years. Resulting test costs have mushroomed accordingly. Scan compression has proven to be a powerful countermeasure to this dilemma, as it has catalyzed reductions in test data volume and test application time, thus reducing test expenses. Yet scan compression has not been an option for companies who are invested in Magma’s Talus Design, because its technology has not matured to the point that it can support scan compression. If these companies want to keep test costs down, they can choose to do without compression or change to new design tools. This paper presents a third choice that integrates Magma’s Talus Design with Mentor Graphics’ Tessent TestKompress to achieve a compression ratio of 100x. The three-step process will be described, including:
SynTest DFT in the Magma Design Flow Author(s): Josh Lee, President and CEO and Sam King, Vice President, ASIC Engineering of Uniquify Inc., and JianPing Yan, Senior Applications Engineer, SynTest Technologies, Inc. Abstract: We will present integration of SynTest DFT tools into the Magma design flow. Uniquify has successfully finished eight projects in the Magma flow using SynTest tools. One large, complex, 15-million-logic-gate design with 495 memories targeted for HDTV applications is in production in 65-nanometer (nm) technology. SynTest tools were used for DFT implementation of BSD, at-speed MBIST, stuck-at and transition ATPG with compression. Memories were tested in 55 groups with MBIST speedup to 500 MHz. OCC was implemented for at-speed testing up to 500 MHz scan test. Test compression was implemented with 20x split ratio for test cost reduction which used 66 scan in/out pin pairs with 1320 internal short chains. ATPG patterns were generated for stuck-at as well as transition faults. The results show that the SynTest tool suite fulfills the testing needs of Magma flow users and delivers high test-quality leading to a very low test cost. Further tighter integration is also presented which will increase the usability.
Session 2: Leveraging Faster, More Accurate Circuit Simulation At-Speed Functional Verification of Complex IOs using FineSim SPICE Author(s): David West, Director of Product Development, Rapid Bridge Abstract: Rapid Bridge designs world class IP solutions that can be overlaid onto standard IO and SOG templates to instantly configure a wide range of high speed PHYs using only metallization. These PHYs can be 6 to 300 IO slots wide, and vary in complexity from simple SGMII complex IOs to 72-bit wide DDR3 or USB2.0 solutions. All PHYs must be rigorously tested using SPICE-level simulation. This presentation will discuss the benefits of being able to use FineSim SPICE on multiple CPUs along with a third-party digital simulator to verify very large complex IOs. A High-Capacity Power Integrity Flow Supporting Inductive Rail Effects with Transistor-Level Accuracy Author(s): Anand Raman, Helic Inc, and George Stamoulis, Chief Scientist and Dimitris Bountas, Vice President of Technology, Nanotropic
Abstract: In this paper, a flow employing Magma, Nanotropic and Helic tools is presented for supply rail analysis (IR and di/dt) that, for the first time, provides transistor-level accuracy with inductive and magnetic rail effects. Helic’s VeloceRaptor is employed for RLCK rail extraction of a design implemented with Talus Vortex. Nanotropic’s engine is a fast gate-level simulator and can draw from a specially-characterized SiliconSmart library. FineSim is employed to co-simulate Nanotropic current signatures and Helic rail models. We demonstrate that this flow provides accuracy comparable to transistor-level SPICE, with coverage of high-frequency rail effects, while processing designs on the order of several millions of gates.
Session 3: Advances in Analog Design and IC Failure Analysis Using the Titan Shape-Based-Router for Actel's Next Generation Flash-based FPGA Product Family Author(s): Lyle Smith, Senior Director of Engineering, Actel Corporation Abstract: The Actel design team successfully used the Titan Shape-Based Router to complete their next-generation FPGA base-platform design tape out. The design has multiple design constraints including river routing, mixed-signal routing with shielding and variable width high-voltage supplies. While prior generations were completed exclusively with manual routing, the use of the Titan system greatly increased the team's productivity while enabling late design changes to be easily accommodated. This presentation will review how this new methodology was developed and used. The Role of Design and Test Methodologies in Integrated Circuit (IC) Diagnosis Author(s): William Ng, Member of Technical Staff, Steven Jacobson, Failure Analysis Manager and Rafael Huerta, Failure Analysis Engineer at National Semiconductor Abstract: Although emphasis is put on design for test (DFT), IC diagnosis is still a challenge. The DFT methodology is often used in IC diagnosis to localize the perspective area on the layout, and in conjunction with failure analysis (FA) techniques to uncover silicon defects.
This paper discusses using Magma’s Camelot CAD navigation and DFT to localize faulty circuitry and software emulation of electrical behavior on the design layout. The technique was used on passive voltage contrast (PVC) imaging, an FA technique to identify silicon defects. Also discussed is a technique in which simulation data of circuit nodes is imported to validate and discriminate benign photon emissions from operating silicon under specified conditions.
Using SiliconSmart ACE and Embedded FineSim Simulator for 28-nm Standard I/O Cell and Memory Characterization Presenter: Haroon Chaudhri, R&D Manager, Magma Abstract: IP characterization at 28 nm and below requires large number of very accurate SPICE simulations. The generated model must be accurate and a characterization tool needs to be able to validate the model quality and consistency. The complexity of SPICE models and circuits has increased significantly in recent years and traditional approaches to simulate and create the model generation database are no longer efficient. This presentation will highlight features of SiliconSmart ACE which can be used to address the needs of next-generation IP characterization, modeling and validation.