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Talus Vortex® is the physical design environment of choice for engineers creating complex systems on a chip (SoCs) at all process nodes and where performance and power management are crucial. It dramatically improves the productivity of designers by providing a range of tightly integrated reference flows and a flexible, integrated infrastructure based on Magma's unified data model. With Talus Vortex, designers can tackle new process technologies and achieve design closure in a fast and predictable manner. The new Talus system enables designers to implement up to 1.5 million cells or more per day on large designs or blocks – with crosstalk avoidance, advanced on-chip variation (AOCV) and multi-mode multi-corner analysis enabled.
The challenges faced by today’s designers require an integrated solution that produces ICs that are correct by construction. From the beginning, Magma has offered a single executable, unified datamodel solution for IC design that addresses these challenges. Unlike other approaches, Talus Vortex is able to deliver extremely fast throughput and efficiency that is ideal for designs at the 28-nm node and for designers creating ever-larger chips. It is also well-suited for customer designs that target applications such as tablets, smartphones and networking and embedded devices that not only provide ever-increasing performance and throughput, but also have extremely tight and diminishing power budgets.
The Talus Vortex implementation system provides a fully integrated netlist-to-GDSII flow for high-performance, complex, low-power nanometer designs. It includes a breadth of leading-edge tools, offering optimization, placement, routing, useful skew clock generation, floorplanning and power planning, incremental RC extraction and a single, incremental timing analysis engine. Built on Magma’s unified data model and employing a silicon-validated strength-based delay model, Talus Vortex raises the bar for capacity, runtime and performance. In conjunction with the comprehensive low-power design capabilities of Talus Power Pro, Talus Vortex provides significant power reductions without sacrificing timing and area.
To address the needs of today’s complex SoCs, Talus Vortex’s netlist-to-GDSII flow is fully multi-mode and multi-corner enabled. All design operating modes and corners are defined at the start of the flow, and the Talus-MX-based implementation system concurrently analyzes and optimizes across all combinations of these modes and corners to produce the best results while minimizing runtime and memory usage.
The Talus MX Router addresses the increasing crosstalk and design rule complexities of advanced process nodes. The natively multi-threaded Talus MX global routing engine is used throughout the flow to aid design closure through advanced congestion control, crosstalk-avoidance-driven spreading and superior layer assignment, resulting in a robust, crosstalk-resistant design. Track-mode optimization is performed earlier in the flow to ensure improved timing convergence. This also helps avoid unnecessary post-route optimization steps where fixing these timing issues is an order of magnitude slower and more complex.
In addition to providing the fastest turnaround time on large designs, Talus incorporates the Talus® Flow Manager™, with its out-of-the-box design flow template system. Engineers can easily tune this reference flow for their specific application. Talus Flow Manager also introduces a comprehensive visual analysis environment, Talus® Visual Volcano, that integrates and presents all design and analysis data via a common, customizable interface.
Key enablers of the ultra-fast and accurate MMMC ability are the Talus MX Timer and Talus MX Extractor. These engines are based on Magma’s next-generation timing and extraction products, Tekton and QCP. The tight integration of this technology as an implementation-mode, fully incremental timer and extractor allows Talus Vortex to handle full sign-off constraints throughout the entire flow and to deliver up to full sign-off accuracy when needed by invoking a Tekton license. This can be accomplished without disrupting the flow or increasing runtime with post-route timing closure engineering change orders (ECOs).
The Talus MX Timer technology provides massive productivity gains throughout the flow, from early in the project design phase when constraint development is a focus, to full MMMC clock tree synthesis and analysis, through to final sign-off validation. By incorporating this ground-breaking technology as its default timing engine, Talus Vortex delivers the fastest implementation throughput, shortens and simplifies the implementation and sign-off process and provides significantly shorter turnaround time.
The Talus MX routing engine efficiently delivers a convergent timing flow through full-flow crosstalk avoidance and focused crosstalk fixing, avoiding overdesign and timing surprises as the flow progresses. The new Talus MX global router offers advanced congestion control and resolution, optimal layer assignment and the ability to natively handle very large designs and those with complex multiple-voltage (MVdd) and hierarchical requirements. The Talus natively multi-threaded MX global router is used consistently throughout the implementation flow as part of the continuous refinement of the design, resulting in a convergent routing solution.
Talus Vortex now performs track-based optimization earlier in the implementation phase. This ensures that crosstalk is more accurately modeled and the relevant paths are fixed earlier, when doing so is more effective and less costly in terms of runtime, power and design perturbation.
The Talus MX routing enhancements also encompass a gridless, pin-access router that ensures that the complex design rules at these advanced nodes are met without iterative refinement. This delivers a simpler out of the box experience for the user and can significantly reduce runtime on even the most complex library styles. Talus Vortex fully supports 45-nm and 28-nm design rules from major silicon vendors and foundries, including complex spacing rules, common run-length rules, stacked-via rules and dense end-of-line rules. Talus Vortex automatically addresses complex antenna rules as well as other process-specific manufacturing requirements such as minimum area rules for vias, metal slotting and timing-driven track-based metal fill, and additionally integrates seamlessly with Magma’s Quartz™ physical verification tools to provide fully timing-driven pattern-based fill. The integrated engines operating on the single data model also enable fast and accurate timing-driven wire spacing and native redundant via insertion.
The Talus Flow Manager provides an out-of-the-box RTL-to-GDSII design flow tuned to deliver optimal results. Designers can easily customize the reference flow and tailor it to their own needs, developing specific flows for various projects or applications. Additional reference flows include templates for the implementation of MVdd, MMMC designs, as well as low-power and high-performance designs. Ease of use and cost of adoption is dramatically improved through the use of these pre-qualified flows for small design teams or large, geographically distributed groups.
The Talus Flow Manager allows designers to customize reference flows.
The Talus Flow Manager includes the Talus Visual Volcano, a technology designed to help designers make better decisions faster. The Talus Visual Volcano analysis environment offers an integrated information interface that allows an engineer to quickly track many parameters of the design, including runtimes, timing, power and area. MMMC design management is made easier by simplifying the control over active versus reported scenarios, and displaying results for all scenarios concurrently. By consolidating this data into HTML charts and graphs, the Talus Visual Volcano saves designers time and improves efficiency by eliminating the need for tedious analysis of log files and textual reports. Block designers, chip integrators or design managers can now all communicate through a common format and make better design decisions as a team.
The Talus Visual Volcano eliminates the need for tedious analysis of log files and textual reports.
MMMC clock tree synthesis is fully integrated into Talus Vortex to ensure that clocks meet both timing and physical goals, and to optimize additionally for power with the Talus Power Pro option. Talus Vortex takes advantage of advanced techniques such as optimal clock gate selection, placement and cloning and un-cloning for better load distribution. It also leverages sophisticated clock algorithms that minimize skew while achieving timing requirements and maintaining design robustness under process variations and environmental differences. With the unique clock-tree visualization interface, users can browse, analyze and visualize aspects of the clock tree with ease.
Talus Vortex also includes an enhanced structural clock tree viewer that allows efficient visual analysis of the entire topology based on depth or level within the clock tree. This tree structure makes it easy to visualize and understand aspects of the clock tree that would otherwise be difficult to conceptualize, making it faster and easier to identify potential skew, balance or latency issues resulting in outlier endpoints.
The clock tree visualization interface is also tightly coupled to the datamodel and can be controlled through the use of Tcl to help highlight any of the numerous metrics that can queried about the design or clock tree.
The structural clock tree viewer speeds analysis of the clocking topology
The clock tree viewer allows designers to overlay metadata on the physically implemented clock tree
Talus Vortex consistently delivers the industry’s highest capacity. This allows users to create larger blocks, saving resources and time by eliminating the need to partition a design into many small blocks. Depending on the complexity of the design, blocks from 2 million to over 5 million cells can be implemented flat with Talus Vortex. This capacity is enabled through Magma’s integrated platform and the single executable of the Talus Vortex system. Traditional solutions require extensive file transfers and translations between different steps of the implementation process, resulting in longer turnaround times.
The full place-and-route flow is multithreaded and able to both analyze and optimize for multiple modes and corners (scenarios) throughout the flow. The use model is simple: supply Talus Vortex with all the mode and corner combinations at the start of the flow, and run. The massive runtime and memory reduction enabled by the Talus MX-based technology ensures a very fast and ultimately convergent flow. There is also a sub-linear runtime profile as scenarios are added which allows Talus Vortex to handle over 100 scenarios during the implementation flow – on a single machine.
Talus Vortex, with Talus Power Pro as an option, provides an integrated power optimization flow, reducing power up to 20 percent over conventional standalone implementation tools while also delivering high performance. This option supports advanced, low-power designs including voltage island support, automatic MTCMOS switch insertion and dynamic voltage and frequency scaling (DVFS). It is the only commercial platform available that supports both the Unified Power Format (UPF) and Common Power Format (CPF). Integrated power optimization capabilities deliver lower dynamic power consumption than conventional synthesis and place-and-route solutions. Talus Vortex’s MMMC low-power clock tree synthesis minimizes the dynamic and static power from clock tree networks. Only optimal cell sizes are used to drive known loads, avoiding unnecessary power dissipation by cells. Balancing input slews to cells through optimal sizing is used to reduce total switching power. Additional power optimization capabilities such as multi-Vt library-based optimization, DFT-aware automatic clock gating, automatic use of integrated clock gating cells in the standard-cell library, detection of synchronously enabled registers and hierarchical insertion of clock gating logic minimize power and improve testability. This automated method significantly reduces design closure time without sacrificing performance.
Talus Vortex is the platform of choice for advanced-node designs, and has been used to tapeout multiple 28-nm designs. Full-flow support for CCS delay models provides the necessary accuracy for the 28-nm process node. The next-generation Talus MX routing technology delivers superior capacity and quality of results. The unrivaled MMMC support enables Talus Vortex to handle large designs without reducing the number of modes or corners used in the implementation flow. Talus Vortex with Talus qDRC can invoke the Quartz DRC engine to implement timing-driven, sign-off quality pattern-based fill that is required to achieve yield targets at advanced process nodes including 45 nm and 28 nm.
Talus Vortex also provides seamless integration of double-patterning checking and routing refinement to address the photolithography challenges at the 20-nm node.
For very large designs and blocks, or to enhance the already industry leading throughput of Talus Vortex, Magma provides the Talus Vortex FX option. Talus Vortex FX, with Magma’s new Distributed Smart Sync™ technology, delivers unmatched throughput for physical design implementation. The Distributed Smart Sync technology intelligently manages the process of distribution and synchronization throughout each of the design steps in the Talus Vortex physical implementation flow. Talus Vortex FX provides over three times higher capacity and throughput, allowing design teams to meet tight schedules without having to invest in additional resources or move to a hierarchical design methodology.Powerful GUI Speeds Design Debug and Exploration
Using the powerful Talus Vortex visualization tool, designers can browse the logical hierarchy and guide partitioning decisions needed for floorplanning. Connectivity-driven visualizations such as fly-lines and clock-domain distribution provide valuable architecture and constraint improvement information. Slack-based timing histograms of critical paths in the built-in timing visualizer allow designers to quickly locate timing problems through direct cross-probing of RTL (with Talus Design), schematic, floorplan or layout. Such analysis speeds identification of missing constraints or exceptions such as false paths or multi-cycle paths. Detailed power reports and maps provide power consumption and distribution information early in the design flow, saving back-end packaging and design re-spin costs.
Cross-probing accelerates quality improvement.
Ease of Use• Library processing • Integrated data model with powerful MX Timer and Extractor • Query DB, GUI, Tcl, reporting • RC extraction for implementation • Comprehensive congestion analysis • Advanced timing visualization • Cross-probing between layout, netlist, schematic, timing GUI and RTL • Built-in reference flow (Talus Flow Manager) and visualization (Talus Visual Volcano)
Timing Closure• Netlist-to-GDSII flow (RTL-to-GDSII flow with addition of Talus Design) • Strength-based physical synthesis • Signal integrity analysis/optimizations (crosstalk noise, crosstalk delay) • Static timing analysis and optimization with OCV, AOCV, common point pessimism removal (CPPR) and crosstalk • MMMC analysis/optimizations with OCV, AOCV and crosstalk • Robust MMMC clock tree synthesis • Early crosstalk avoidance flow • Surgical wire optimization for timing and DRCs • Rapid timing closure with SDF back annotation • Concurrent MMMC aware setup/hold/limit/DRC optimization • Incremental extraction, timing • Scan chain reordering • Full-flow multi-threading (with Talus MCPU license)
Advanced Nodes• 40- and 28-nm routing • Full-flow CCS optimization and analysis • Wire spreading and widening (basic or CAA) • Recommended end-of-line extensions • Redundant via insertion • Cell yield optimization • DFM soft rules • Timing-driven metal fill [density or chemical-mechanical polishing (CMP)] • Pattern-based metal fill (with Talus qDRC) • Automated SPICE delay and crosstalk noise correlation• Emulated metal-fill extraction
Low Power• Embedded static power analysis • Multi-VT leakage optimization • MVdd with full UPF/CPF support (with Talus Power Pro)
Advanced Placement and Optimization Features• Multi-height cell placement with power/ground rail sharing Advanced Clock Tree Features• Useful/zero skew • Low-power clock tree implementation using clock cloning/un-cloning and advanced clock gating. • Inter-clock skew minimization • Multiple clock domains • Automatic gated-clock checks • Advanced clock tree viewers • Support for complex non-default rules and clock shielding
Advanced Routing Features• Virtual gridless router • Interactive bus routing • Complete ECO support • 28-nm design and manufacturability rules • Built-in polygon-based DRC engine • DFM-aware routing • Crosstalk and timing driven Crosstalk Delay Analysis• Timing window-based filtering • Capacitance-based filtering • Logical correlation filtering • Slew-based crosstalk delay prevention • Automatic timing window convergence
Inputs• DEF (floorplan),Verilog (netlist), .lib, SDC, SPEF, LEF, GDSII, UPF, CPF, Volcano™ (Magma format)
Outputs • DEF (floorplan),Verilog (netlist), .lib, SDC, SPEF/DSPF, LEF, GDSII, Volcano (Magma format), UPF, HTML
Platforms • Linux, Sun