Talus Design

Talus® Design is a full-chip synthesis environment that enables rapid development of RTL and chip-level constraints throughout the design process without sacrificing the quality of design or delivery schedule.This integrated environment dramatically improves the productivity of chip architects and logic designers by automating data-path synthesis and floorplan generation for prototyping. Talus Design and Talus Vortex together enable any size design to be implemented from RTL to GDSII in a predictable fashion.

Full-featured RTL, DFT and data-path synthesis for smaller area, higher performance and lower power.
Fully automated macro placer flow with underlying RTL synthesis and optimization technology enables rapid exploration of the design space with handoff to the physical implementation flow, and provides a predictable path to design closure.
Timing and congestion-driven macro legalization removes need for block-level floorplanning.
Early RTL, DFT and netlist checks result in accelerated problem detection and correction, rapidly improving the quality of input.
Significant improvement in ROI achieved through 30 percent reduction in turnaround time and 20 percent reduction in development cost.
Very large capacity and fast run times allow complexity scaling without compromising productivity, requiring additional engineering resources or adversely affecting schedules.

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Featured Resources
- White Papers
  - Hydra: Automated Floorplan Synthesis
  - Package-Aware I/O Planning
- Webinars
  - Fastrack/Talus
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