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Quartz™ Time provides sign-off verification for timing and noise and is a perfect companion to Magma’s integrated Sign-off in the Loop™ ecosystem. Quartz Time addresses the complex timing problems associated with 90-nm and finer processes through concurrent multi-mode, multi-corner and OCV analysis, ECSM support, multi-voltage and IR-drop-induced delay analysis that accurately reflect the effect on timing.
As process technologies advance to 90 nanometer (nm) and below, new design and analysis challenges arise. The complex interdependencies of new nanometer effects such as signal and power integrity, multiple corner validation and on-chip variation can no longer be analyzed in isolation. The growing design complexity enabled by 90-nm processes also creates enormous capacity and runtime challenges. As a result, turnaround time and costs are rising dramatically. The traditional delay model is nearing the end of its evolution. Nanometer designs require new modeling techniques for cell and interconnect delay that can accurately support multiple voltage levels and IR drop effects.
Quartz Time is Magma’s standalone sign-off verification solution for gate-level designs. Based on technology within the industry-proven Magma RTL-to-GDSII design system, Quartz Time combines static timing, crosstalk delay, crosstalk noise (glitch) and IR drop-induced delay analysis to provide a comprehensive sign-off solution. It provides the most sophisticated static timing and signal integrity analysis technology and ensures that next-generation IC designs get right to market, right on time and at the right price. Quartz Time supports the leading-edge ECSM delay models and offers concurrent multi-corner analysis to help design teams achieve predicted timing.
Quartz Time provides a comprehensive sign-off verification solution that combines static timing analysis, accurate RC delay calculation, advanced modeling and timing debug that is the perfect companion to Magma’s Sign-off in the Loop ecosystem. Quartz Time accurately analyzes crosstalk delay, crosstalk noise (glitch) and IR drop delay effects and, combined with industry-leading runtime performance and capacity, enables designers to achieve first-pass silicon success and fast time to market on their multimillion-gate designs.
Quartz Time accounts for the interdependencies of timing,signal integrity and power.
Multi-mode timing analysis allows concurrent analysis and optimization of multiple modes, eliminating iterations for timing closure. A design can have multiple modes of operation and each mode can have different, even conflicting, constraints. The traditional approaches to analyzing multiple modes independently are cumbersome and iterative. Quartz Time’s analysis engine is aware of the interrelated effects of multiple modes and can make decisions that satisfy timing constraints for each mode, completely eliminating iterations.
Quartz Time utilizes the proven Blast Noise engine for precise signal integrity analysis. It uses advanced analysis models, intelligent filtering, slew propagation, logical correlation of signals and timing window convergence techniques to accurately predict SI problems while minimizing false errors. It uses Liberty noise library information for noise calculation, detection and propagation. Crosstalk noise problems are modeled using a highly accurate 2-pole noise model which models both aggressor and victim nets. Accumulation models are used to account for multiple aggressors on a given net. For crosstalk delay, Miller capacitances, based on either a static or a slew-based dynamic model or an accurate waveform-based model, are calculated. The delays calculated are applied automatically to static timing analysis to account for crosstalk delay.
Quartz Time includes a powerful viewer with strong debugging and cross-probing capabilities, which minimizes the time it takes to identify timing issues. Timing and clock histograms are some of the basic handles in the viewer for easy detection and examination of the failing paths. Quartz Time generates detailed timing reports which are broken up into individual cell/wire delays in the viewer. It also offers a graphical view of the impact of crosstalk delay along the path to clearly distinguish the individual effects.
Design teams have traditionally relied upon one set of tools for implementation and another set for sign-off analysis. While this separation enables an advantageous trade-off with respect to accuracy versus runtime, it also requires corrective iterations when discrepancies are found during sign-off analysis.
Magma’s integrated Sign-off in the Loop ecosystem offers ASIC designers flexibility, providing an ecosystem of products that can be deployed either as standalone tools for ASIC customer validation, or with extraction, timing and noise capabilities that are integrated into Magma’s RTL-to-GDSII design flow. Quartz Time fits perfectly in that ecosystem as a standalone tool for timing and noise sign-off verification.
Quartz Time streamlines the flow and eliminates the time-consuming hand-offs between a vendor and customer by sharing its analysis engine with the implementation tools
Quartz Time shares its engine with Blast Fusion QT and Blast Noise.
Quartz Time provides comprehensive nanometer technology support.
Blast Fusion QT, Blast Noise and Blast Rail. Designed to complement the Sign-off in the Loop ecosystem, Quartz Time extends support to independent signoff verification flows that do not require a full Blast Fusion system, such as ASIC customer use.
Implementing multimillion-instance nanometer designs requires very efficient yet highly precise delay calculation and modeling. There is significant variation between near-end and far-end waveform shapes due to resistive interconnect, receiver input capacitance and the driving point admittance seen by the driver. There is also an increasingly non-linear cell response noticed in voltage and process variation. To achieve the highest degree of accuracy using ECSM, the driver is modeled as a time-dependent nonlinear current source and the receiver as an input-slew-dependent capacitance. Magma’s SiliconSmart™ tools provide this advanced characterization capability for generating ECSM libraries. Quartz Time can perform delay calculation based on both Liberty (.lib) and more accurate ECSM format libraries.
OCV effects, including removal of pessimism caused by common paths, must be addressed in nanometer geometries. OCV is caused by variations in voltage and temperature, in line widths across the chip, in doping densities, in charge accumulation in gate oxides and more. Quartz Time takes OCV effects into account during timing analysis and integrates them with crosstalk delay analysis. Multi-corner timing analysis is used to resolve different timing problems that appear at different processes, voltages and temperatures. These differing conditions make it difficult and time consuming to identify the single worst corner-case and to fix violations. Quartz Time’s multi-corner timing analysis generates timing constraints that combine the effects of multiple operating conditions into a merged corner. Timing analysis is then run on the merged corner to enable high-capacity design closure.
Static Timing Analysis• Enhanced ECSM delay calculator• Complete 1.4 SDC support with extensions• Hierarchical constraint support• Load/store timing data• SPICE deck generation for qualification
Nanometer Design Support• OCV analysis• Multi-mode analysis• Multi-corner analysis• Noise/IR drop effects on timing analysis• Hierarchical analysis
Crosstalk Noise Analysis• Hierarchical noise analysis• Highly accurate reduced-order model noise calculation method• Timing window-based filtering• Capacitance-based filtering• Support for Liberty noise format
Crosstalk Delay Analysis• Timing window-based filtering• Slew-based crosstalk delay prevention• Automatic timing window convergence• OCV with crosstalk analysis
Voltage Drop-Induced Delay• Instance-specific derating• Incremental timing to ensure convergence
Visualization for Design Exploration• Advanced Timing Viewer – Timing Histograms – Constraint checking/editing – Detailed path reporting and graphical breakup: cell delay, wire delay, crosstalk delay – Cross-probe timing paths against floorplan, schematic and layout – Graphical representation of noise violations – Clock viewer for viewing histograms of insertion delay/skew for all clock skew groups in the designInput• Verilog (netlist),.lib,SDC,SDF,SPEF,Volcano Magma format
Output• Timing reports,noise reports,.lib,SDC,SDF, Volcano (Magma format)
Platforms• Sun Solaris, Linux