Magma in the News - 2006 

December

• 12/13 Magma enhances the business focusing on analog and DFM, Digital Times Korea (in Korean)
• 12/13 Magma enhances business focusing on analog and DFM, EDN Korea (in Korean)
• 12/13 Magma Korea holds “EDA Business Strategy Press Conference”, Yon Hap News (in Korean)

November

• 11/30 Magma names user conference chairman, EE Times
• 11/28 Magma buys Knights for chip fab analysis, Electronic Weekly
• 11/20 Magma Gains Manufacturing Links with Fab Analysis Biz Buy, Electronic News
• 11/20 Magma buys yield analysis pioneer, EE Times
• 11/16 RTL-To-GDSII Flow Encompasses Embedded Memory Test And Repair, Electronic Design
• 11/14 IC Design Is At An Important Transition, Electronic Design
• 11/13 Donation speeds statistical library format, EE Times
• 11/10 Low Power Raises the Heat, Electronic News
• 11/07 EDA's hope is enabling cheaper design, Madhavan says, EE Times
• 11/02 Cadence rivals unimpressed with power standards offer, EE Times

October

• 10/23 Nanometer ICs have stringent testing requirements, EE Times
• 10/19 Magma affirms design for test strategy, EE Times
• 10/09 Magma gets high marks in EDA market study, EE Times
• 10/02 Striking a balance for low-power designs, EE Times

September

• 09/28 FPGAs Ride Tools Into ASIC Territory, Electronic Design
• 09/25 Support Builds For Accellera's Unified Power Format Specification, Electronic Design
• 09/21 Chip designers work to tame electromigration, EE Times
• 09/21 Magma contributes to Accellera power standard effort, EE Times
• 09/19 Spice simulator offers speed, capacity increase over competitors, EDN
• 09/18 Magma Spice circuit sim tool claims top speed, EE Times
• 09/14 Accellera launches 'unified power format' effort, EE Times
• 09/08 Magma Goes Mainstream, EDN
• 09/08 Letter: EDA has leadership, needs more, EE Times

August

• 08/28 A Flexible Solution for Implementing Structured ASIC Designs, SOC Central
• 08/17 Integrated DFM Technology Takes Aim At 65-nm Designs, Electronic Design
• 08/17 Sifting the DFM Players, EDN
• 08/16 Arrays narrow platform ASIC, FPGA gap, EE Times
• 08/16 GUC Adopts Magma's RTL-to-GDSII Design Flow, EDN Asia
• 08/14 Revelations from DAC, EE Times
• 08/11 Magma Integrates TSMC's Reference Flow 7.0, EDN Asia
• 08/08 DAC Report: Magma Demonstrated New Implementation Environment Talus, EDA Express (in Japanese)
• 08/07 Rival efforts tackle low-power standards, EE Times

July

• 07/31 True DFM/DFY Solutions Require More Than OPC And DRC, Chip Design
• 07/31 SIMULATION: Acquisition to bear 'trimode' fruit, EE Times
• 07/25 TSMC Announced Reference Flow 7.0 for 65nm, with STA, EDA Online (in Japanese)
• 07/25 Roy Jewell interviewed from DAC by EE Times' Richard Goering, EE Times TV
• 07/24 EDA, IP vendors seek statistical library format, EE Times
• 07/24 Customer Tapeout Success is Primary Focus, On Design Radio.com
• 07/24 Is Synopsys’ Statistical-timing Tool Ready for Prime Time?, EDN
• 07/23 Magma offers “tri-mode” circuit simulator, EE Times
• 07/18 Magma Design Flow Targets 65nm, ElectronicsWeekly.com
• 07/18 Magma offers statistical timing analysis methodology, EE Times
• 07/17 Buzz@DAC.2006 v2, EDACafe.com
• 07/17 TSMC unveils 65-nm design reference flow, EE Times
• 07/17 Magma rolls integrated tool flow for DFM, EE Times
• 07/13 Max's Chips and Dips: Magma's Automated Chip Creation Now Package-Aware, Chip Design
• 07/01 Heavy Vetting: Boards of Directors Now Want to Talk to Would-be CFOs – and Vice Versa, CFO Magazine

June

• 06/26 Cooley census: Magma users prefer anonymity, EE Times
• 06/19 Chip designers feel the heat, EE Times
• 06/16 Magma Expands in India, Asia Times
• 06/06 Magma plans second R&D center in India, EE Times
• 06/01 Burn Baby, Burn, Electronic Business
• 06/01 Integration paces point-tool development, Test and Measurement World

May

• 05/16 Running start helps clear 90nm hurdles, EE Times Asia
• 05/15 EDA vendors line up to support Virtex-5, EE Times
• 05/15 Optimization techniques rein in IC power flow, EE Times
• 05/15 TSMC DFM format empowers fabless design, EE Times
• 05/15 ARM Launches Next-Generation Processor for Deeply Embedded Systems, Finanz Nachrichten.de
• 05/08 Automated Chip Creation, SOC Central
• 05/02 Innovation Big and Small - Chapter Two, FPGA and Structured ASIC Journal
• 05/01 Magma joins OpenAccess, EE Times

April

• 04/25 Magma's Talus tool cuts design cycle, costs, EE Times India
• 04/25 Role of IBM engineer pivotal to Synopsys-Magma case, EE Times
• 04/25 Running start helps clear 90nm hurdles, EE Times Asia
• 04/24 EDA Tools Claim True Automation of IC Design, Electronicstalk
• 04/22 Magma Unveils Talus - Offering Unequaled Automation for Nanometer IC Design, Newswire Today
• 04/21 Magma Launches Automation Platform for Chip Design, newindpress.com
• 04/21 Synopsys, Magma court battle set to tip-off Monday, EE Times
• 04/21 Magma Unveils Automation Software for Nanometer IC Design, domain-b.com
• 04/20 Targeting 65nm and Below, Magma Innovates New EDA Implementation, Nikkei EDA Online (in Japanese)
• 04/19 Talus Targets RTL to Tape-Out, Test & Measurement World
• 04/18 Magma Announces New Integrated RTL-to-GDSII Environment, “Talus” - Promising True Design Automation, EDA Express (in Japanese)
• 04/18 Magma Unveils New Automation for Nanometer IC Design, Test and Measurement.com
• 04/17 Magma tool suite promises push-button compilation, EE Times
• 04/17 IP Implementation Platform Promises Two-Day Full-Chip Turns, Electronic Design
• 04/13 IP From the Implementation Perspective, Electronic Design
• 04/12 EDA industry needs to take responsibility, Madhavan says, EE Times
• 04/01 Startups Grow Up, Electronic Business

March

• 03/31 Madhavan to keynote OpenAccess+ Conference, EE Times
• 03/30 Chartered, IBM, Samsung announce 65-nm DFM support, EE Times
• 03/16 EDA Industry Urged to Stick to Standards, ElectronicsWeekly.com
• 03/15 Unified Data Model Critical to Addressing Sub-Nanometer DFM/DFY Issues, Chip Design
• 03/14 What Do You Tell Them?, FPGA Journal
• 03/13 Magma Announces Integrated Advanced Low-Power Reference Flow, EDN Asia
• 03/07 3 Big Layout EDA Vendors Announced Their Design Flow for 90nm IBM-Chartered, Nikkei EDA Online (in Japanese)
• 03/07 Si2 Releases ECSM 2.0 Standard for Design Libraries -- First Deliverable from Open Modeling Coalition, Business Wire
• 03/06 Vendors warm to SystemVerilog, EE Times
• 03/03 Magma Announces Integrated Advanced Low-Power Reference Flow for IBM-Chartered 90-Nanometer Common Platform, PR Leap
• 03/02 EDA startup rolls 'all inclusive' cell characterization tool, EE Times
• 03/01 Passage to India, Electronic Business

February

• 02/27 Firms tout low-power, 90-nm Common Platform flows, EE Times
• 02/24 IC Design Consultancy Commits to Magma, Electronicstalk
• 02/22 Magma, Rio Design ink OEM agreement, EE Times
• 02/20 Huge FPGA synthesis gap seen, EE Times
• 02/20 Drawing on Software, The Hindu Business Line
• 02/13 Mentors teach skills, hard and soft, EE Times
• 02/07 Multithreading Core Aims to Cut Embedded Costs, Electronicstalk
• 02/02 Co-Design: EDA Vendors Are Helping IC and Package Designers More Effectively Work Together, EDN

January

• 01/31 Status Quopia: Structured ASIC Captures Mindshare, FPGA and Structured ASIC Journal
• 01/30 Chip tool has bump radar, EE Times
• 01/30 A Joint Effort, The Hindu Business Line
• 01/23 Five join Magma partner program, EE Times
• 01/23 Chip road map calls for overhaul in EDA, EE Times
• 01/05 It's 2006, Are You Ready for 65-nm?, TechOnLine
• 01/02 EDA execs: ESL, DFM will stand out in lackluster '06, EE Times

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